Shift register unit is a unit-circuit of a gate driver on array (GOA) circuit for providing a gate drive signal to a corresponding gate line to drive a row of pixels on a display panel for imago display. A conventional drive scheme is a so-called JUST scheme in which multiple clock signals, such as a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3 or CLK4, are sequentially inputted with turn-on voltage level into the shift register unit. At the moment when a clock signal with turn-on voltage level ends its input phase, a next clock signal with turn-on voltage level immediately starts its input phase (without any overlap) for adjusting each signal cycle and possible interval between adjacent signals. As an output from an output thin-film transistor (TFT) of one-stage shift register unit, which is originated from a clock signal CLKn, is inputted into a next-stage shift register unit, a coupling noise may be generated in the gate drive signal associated with the particular driving clock signal. For example, undesired multiple-outputs of gate drive signals may occur. Conventional shift register includes a TFT for controlling pull-down node potential to prevent such incorrect multiple-outputs of gate drive signals. But as this TFT is deteriorated over the driving voltage and is heated over time, the reliability of the TFT becomes poorer and the coupling noise issue will be worse, causing image flickers or other malfunctions in the display panel based on the conventional shift register unit. The longer of the clock signal driving time used in the conventional shift register unit, the earlier these malfunctions will occur.